Basic Problems with altlvds_rx ipcore on CycloneV

Dear everyone, I have to receive LVDS data stream based on altlvds_rx on cycloneV device. LVDS data paires are 500Mbps with accompany 250MHz clock(DDR mode). I set following parameters in the ipcore:

deserialization factor: 10

data rate: 500Mbps

clock frequency: 250MHz

phase alignment of rx_in to rx_inclock: 90.0

At the meantime I also set following constraint in sdc:

create_clock -name lvdsrx_inclk -period 4.000 -waveform { 0.000 2.000 } [get_ports "rx_inclock"]

After compilation, I find that there are hold timing errors inside the altlvds_rx ipcore:

http://www.alteraforum.com/forum/attachment.php?attachmentid=9720&stc=1

The strange thing is that all the problem is inside the altlvds_rx itself, and I have no idea how to make a change.

Note that I have already set fitter to optimize hold timing for all paths.

Question:

1. Should I create lvdsrx_inclk clock in SDC? This is required or not?

2. If yes, how to correct this timing error?