AXI - Avalon Error in Qsys/Platform Designer

Hello,

Has anyone had any success in using AXI w/ Quartus? Particularly with Qsys/Platform Designer? Our team is developing an infrastructure of cross-platform peripherals and we’ve chosen AXI4 as our common interface.

IntelFPGA’s literature is pretty thorough and I’ve done quite a lot of reading on the subject and I have confidence this can work, but I’m encountering an issue with Qsys failing to generate the full set of adapter logic between the AXI and Avalon domains. When generating synthesis products (Verilog) from the system, I receive the following message:

“error: _adapter_ “avalon_st_adapter” instantiated_adapter “_adapter_0””

I’ve tested this on Quartus Prime v15.0, 16.1, 17.0 and 17.1—all have the same error. This is with a minimal system consisting of a single AXI Bridge, Clock Source and (thiny) On-Chip Memory. To me, it looks like the TCL script responsible for traversing the system is incorrectly parsing something in the system (noting the extraneous, misplaced underscores). I’ve been googling the issue for days and have come up empty. Thanks in advance for any insight.