Forum Discussion
dennis4
New Contributor
New Contributoravl_read_data_vaild question
I use the IP DDR3 SDRAM to control TSOM FPGA SDRAM,the avl_write_req is zero,but why avl_read_data_valid is always zero,can anyone tell me how the avl_read_data_valid works? the same code I can work ...
AdzimZM_Altera
Regular Contributor
Regular ContributorHi,
The readdatavalid signal will indicate the data is ready after the read signal is requested.
You need to read through the Avalon Interface Specification document to get some ideas on the read and write transfer of Avalon Memory Mapped interface.
Here the link for instance: https://www.intel.com/content/www/us/en/docs/programmable/683091/20-1/pipelined-read-transfer-with-variable.html
Are you using TSoM Evaluation Kit?
If yes, does the kit working normally with the DDR3 example design from the TSoM Evaluation Kit CD (rev.B Hardware) resources?
Regards,
Adzim
