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dennis4's avatar
dennis4
Icon for New Contributor rankNew Contributor
3 years ago

avl_read_data_vaild question

I use the IP DDR3 SDRAM to control TSOM FPGA SDRAM,the avl_write_req is zero,but why avl_read_data_valid is always zero,can anyone tell me how the avl_read_data_valid works? the same code I can work in HPS.

Hdl

3 Replies

  • AdzimZM_Altera's avatar
    AdzimZM_Altera
    Icon for Regular Contributor rankRegular Contributor
    3 years ago

    Hi,

    The readdatavalid signal will indicate the data is ready after the read signal is requested.

    You need to read through the Avalon Interface Specification document to get some ideas on the read and write transfer of Avalon Memory Mapped interface.

    Here the link for instance: https://www.intel.com/content/www/us/en/docs/programmable/683091/20-1/pipelined-read-transfer-with-variable.html

    Are you using TSoM Evaluation Kit?

    If yes, does the kit working normally with the DDR3 example design from the TSoM Evaluation Kit CD (rev.B Hardware) resources?

    Regards,

    Adzim

  • AdzimZM_Altera's avatar
    AdzimZM_Altera
    Icon for Regular Contributor rankRegular Contributor
    3 years ago

    As we do not receive any response from you on the previous reply that we have provided, I now transition this thread to community support. Please login to ‘https://supporttickets.intel.com’, view details of the desire request, and post a feed/response within the next 15 days to allow me to continue to support you. After 15 days, this thread will be transitioned to community support. The community users will be able to help you on your follow-up questions.