Forum Discussion
New ContributorAvalon Verification IP example avlmm_1x1_vhdl not working in Questa Intel FPGA Edition
Hi,
Please follow the debug steps below:
1.In the run_simulation.tcl script, add this command set USER_DEFINED_ELAB_OPTIONS -novopt to simulate without optimization.
2.Then, in the command prompt type vsim -suppress 12110 to invoke the Questa simulator GUI.
3.Then, do run_simulation.tcl script again and should see the full complete simulation.
Thanks,
Best Regards,
Sheng
p/s: If any answer from the community or Intel Support are helpful, please feel free to give best answer or rate 4/5 survey.
Occasional ContributorHello.
The newest revision of QuestaSim does not accept -suppress switch.
The problem is that the QuestaSim optimizer flashes the delta-events. If you are using multilanguage QuestaSim, the solution is to make little tunning in the "altera_avalon_mm_master_bfm_vhdl_wrapper.sv" file:
1) Change timescale resolution `timescale 1ps / 1ps
2) In line 519 add "#1", like:
always @(mm_master.signal_all_transactions_complete) begin
events[MM_MSTR_EVENT_ALL_TRANSACTIONS_COMPLETE] = 1;
#1 events[MM_MSTR_EVENT_ALL_TRANSACTIONS_COMPLETE] <= 0;
end
It will solve the problem. You can save the custom file and each Platform Design reconfiguration, just replace the "altera_avalon_mm_master_bfm_vhdl_wrapper.sv" file with a patched one.
Good Luck
Igor
- powARman
Hello @IgorKa,
I tried your proposal, I had to add the #1 to all the events to get it working, and I also had to apply the same changes to the slave wrapper file. After doing that, I could run my simulations successfully without having to disable optimizations. Thank you very much.
I created two sed commands to do the replacement automatically after generating the files:
sed -i "s/\(^.*timescale 1\)ns\( *\/ *1\)ns\(.*$\)/\1ps\2ps\3/g" avlm_avls_1x1/simulation/submodules/*_wrapper.sv
sed -i "s/\(^.*\)\(events\[.*\] *<= *0;\)/\1#1 \2/g" avlm_avls_1x1/simulation/submodules/*_wrapper.svBest regards
Andreas
