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Altera_Forum's avatar
Altera_Forum
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14 years ago

Avalon MM templates in Qsys

Hi,

Has anyone successfully implemented an Avalon MM master template in Qsys?

I'm seeing a warning which I didn't see in SOPC Builder for the same system which I ignored initially:

"Conduit interface can't have an associated clock"

I've subsequently discovered that my data and control signals are not being passed thorugh the conduit into Qsys. If it was my own component I would go into Component Editor and change the interface propoerties but the master templates don't allow you this option - the "edit" button is greyed out.

Any suggestions?

John

26 Replies

  • Altera_Forum's avatar
    Altera_Forum
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    14 years ago

    I'd rather edit the component's _hw.tcl file directly.

    Component editor is not very smart in managing things created with older tools.

    I think you only need to change a few lines according to Qsys syntax.
  • Altera_Forum's avatar
    Altera_Forum
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    14 years ago

    Sounds like the conversion on the backend isn't working properly. Open up the .tcl file and look for the deceleration of the conduit and remove the part that is associating the clock interface to it. I would save a copy of it since one of these days (don't know when) I plan on removing those templates and replacing them with better ones.

  • Altera_Forum's avatar
    Altera_Forum
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    14 years ago

    Thanks Guys,

    I amended the hw_tcl file for the template, removing the clock association and that got rid of the error messages in qsys. The template is still not working but now I'm not sure why - the investigation continues....

    Thanks for your inputs,

    John
  • Altera_Forum's avatar
    Altera_Forum
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    14 years ago

    Just to close off on this one, I've analysed the master template signals in signaltap and have found that no avalon signals are being generated at all by the template despite the correct signals being sent to the template.

    I have decided to stop trying to use the master template and will instead design my own custom component in Qsys.

    BadOmen - if you do update the master templates, could you please let me know?

    Thanks again,

    John
  • Altera_Forum's avatar
    Altera_Forum
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    14 years ago

    Hmmm that's odd. I haven't really been following the templates over the last few years so it could be that they broke somehow in later versions (why? no idea).

    You can use the masters from the mSGDMA to do that same thing in Qsys, just export the streaming ports which provide the same sort of as the master template. There are more signals to control since it offers a lot more functionality than the master templates have. Each master has a pdf document which will describe what all the control signals do. You could also look at the dispatcher block since I have small pair of modules that break out the signals as well.

    Alternatively you could use the read and write masters from the Qsys tutorial design. They have a similar feature set as the master templates and are optimized to run really fast. They don't come with documentation but it should be easy to figure out from the comments in the HDL.
  • Altera_Forum's avatar
    Altera_Forum
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    14 years ago

    I've now tried writing my own simple Avalon MM master component to write and read a single word of data from DDR2 memory using the Altera high performance memory controller.

    During the write transaction, the memory controller core does not assert waitrequest and it appears as though the write transaction completes according to the Avalon MM spec. However, the memory controller does not exert mem_we_n or mem_cs_n.

    During the read transaction, the memory controller asserts waitrequest in response to the read signal and it remains high indefintely and doesn't complete the transaction.

    I guess I'm doing something wrong in either the verilog control code or the qsys configuration. I would really appreciate it if anyone has time to look at the attached files and offer any advice.

    Thanks,

    John
  • Altera_Forum's avatar
    Altera_Forum
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    13 years ago

    hey

    you got a work around for this templates u can upload here? im facing the same problem now i want to add a master to acces ddr3 ram.

    Rene
  • Altera_Forum's avatar
    Altera_Forum
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    13 years ago

    Does this issue happen in simulation? If so are you waiting for the calibration phase to complete (it takes around 250us if I remember correctly). So if the controller is still calibrating a few read commands will be allowed in then waitrequest will assert for around 250us and then finally the reads will return.

    If you are looking for similar functionality as the master templates I recommend using the master components in the Qsys tutorial example design. The interface to control them is a little different (ST sink that accepts transfer requests) but they should work a lot better. Similarily the modular SGDMA up on the wiki would be another alternative if you need more features in the master hardware.
  • Altera_Forum's avatar
    Altera_Forum
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    13 years ago

    Hey,

    i use the template to get an block in QSYS now im tryin to interact with the user/control interface.

    wire [31:0] data [0:4]; // 4 Byte Datenfeld

    wire control_fixed_location;

    wire control_write_base;

    wire control_write_length;

    wire control_go;

    wire data_to_buffer;

    assign control_fixed_location = 1'b0;

    assign control_write_base = 32'h0FFFFFAA;

    assign control_write_length = 4;

    assign control_go = 1'b0;

    assign data_to_buffer = 1'b0;

    assign data[0] = 32'hAABBAAFF;

    assign data[1] = 32'hAABBAAFE;

    assign data[2] = 32'hAABBAAFD;

    assign data[3] = 32'hAABBAAFC;

    always @(posedge button_pio[0])

    begin

    assign data_to_buffer = 1'b1;

    # 1 assign data_to_buffer = 1'b0;

    end

    always @(posedge button_pio[1])

    begin

    assign control_go = 1'b1;

    # 1 assign control_go = 1'b0;

    end

    Is that code right or did i make some mistakes? Im not sure how long to toogle control go and data_to_buffer. Is one clk cycle right?
  • Altera_Forum's avatar
    Altera_Forum
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    13 years ago

    I assume you want to push a button for a transfer to start? If so then I would first debounce the button signal, and then use an edge detect on the debounced signal. This will generate a clean one clock cycle pulse into the go bit.

    Using the positive edge for a push button directly is not a good idea because A) it's not a clock and B ) push buttons typically have a lot of bounce so when you push it it'll probably progress high ---> low ---> high a few hundred/thousand times.