Avalon MM templates in Qsys

Thanks BadOmen

Here is what I can say :

1) The phsyical memory and the interface are likely to be OK: the FPGA kit comes with its own verification design and a test app program to control it. When I ran the board test applicaiton it was able to read/write successfully from/to the QDR SRAM.

2) Aslo, the design is constrained and meets timing - no warnings etc..

Actually, nither read nor write work. When I do a 'write', control_done is asserted (lookijng at signal tap), but wait request goes high and stays high, so that when I do a seocnd write request, the 'control done' goes low and does not go high again.

For the read operaiton, I never get 'control done' back and wait request to the read master also gets asserted indefinitely.

Anythie else you can suggest?

Thanks!