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I've now tried writing my own simple Avalon MM master component to write and read a single word of data from DDR2 memory using the Altera high performance memory controller.
During the write transaction, the memory controller core does not assert waitrequest and it appears as though the write transaction completes according to the Avalon MM spec. However, the memory controller does not exert mem_we_n or mem_cs_n.
During the read transaction, the memory controller asserts waitrequest in response to the read signal and it remains high indefintely and doesn't complete the transaction.
I guess I'm doing something wrong in either the verilog control code or the qsys configuration. I would really appreciate it if anyone has time to look at the attached files and offer any advice.
Thanks,
John
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Hi,
I've run into the same (similar) problem with trying to use QDRII SRAM interface (AValon-enabled) in Qsys with Aletra's MM master read/write templates. The sims run correctly, but when I go to hadware, write transactions complte OK, but reads never return (control_done signal goes low upon asserting 'go' and never goes high again). I take it that the waitrequest from the fabric is staying high. Any clues?
The fifos are defined size 32 (someone had an issue with size '4'). In the sims the interface takes a while to complete calibration. Is it possible the same happens in real life, i.e. calibration never succeeds?
I'm using straix iv 100g dev board.
Thanks
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