Avalon MM "sniffer" connections in QSYS

Up and running ... choose option 1) where I have an Avalon MM "bridge" that acts as a bus monitor. ( slave in -> master out ).

Thanks to Dave's sample testbench, I was able to run a 32 bit simulation, followed by a 64 bit simulation. After that

I added the 64 bit bus monitor component to the actual design and ran some simulation , but I need to do some more

work on the PCIe RC testbench to generate the necessary patterns. The current testbench stores addresses and I want to

store random data ... which should not be too much work.

The other monitor has to check PCIe read completions for reads initiated by NIOS II. I believe this will be a dual of the above there

PCIe BAR master writes were monitored.

In the lab, I see the "data" pattern match output to a LED on the scope while running the producer / consumer test.

Thanks Bob.

Once I have both monitors in place , one take pattern match inputs via conduits and track both activities via a state machine that can then report errors to NIOS II via a regular slave interface. The regular slave interface can also define "data" and "flag" patterns

per the producer / consumer test definition.