Forum Discussion
Altera_Forum
Honored Contributor
11 years agoI completely misunderstood this ... I was hoping that my sniffer would be on the side of the existing logic and as a bridge , would just pass on to the "other side" all MM tranactions from a slave. When I ran that in the simple qsys_vip environemnt, I still get an error where the sniffer slave address map can't conflict with other slaves that are real and no transactions get to the sniffer.
What you say above make sense in I have PCIe_BAR1_MM _master -> IMEM and PCIe_TX_MM_slave -> IMEM . The BAR1 master has writes that I want to monitor with respect to the TX which has read completions. So .. I think there are 2 alternatives. 1) mm_slave-> mm_master bridge/ monitor for the BAR1 and mm_slave -> mm_master bridge/ monitor for the TX . OR 2) Just edit the top level rtl and probe the IMEM data write and the NIOS data read ports with a non-Avalon MM component and somehow get that pushed back into simulation. This approach seems more straightforward, but means there is a manual operation. The sniffer would still be a Qsys component with a MM slave port to allow NIOS to read tracking state machines and set up data only pattern matching values but there would be IMEM and NIOS data in ports with the necessary controls as qualifiers. This seems simpler since the sniffer is more "passive" with respect to the system and no new bridges are involved. Any ideas on the best approach ? Thanks.