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I modified my "sniffer" to match the address and data widths and believe the simulation model is only generated if there are zero errors and zero warnings at the Qsys generate step. I may have been thinking warnings were Ok when they are not.
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Maybe it depends on the specific warnings you are dealing with? But in general, your statement is not true: Qsys will generate simulation and testbench files if warnings are present. It won't do anything if errors are present.
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I will work with what I have and need to get the "sniffer" slave be able to monitor all traffic from a given master. The address is really a don't care since I am only intereated in write data and completion data at the "sniff" but I need to get Qsys to honor the BridgesToMaster = 1 attribute ... I really need that to happen and not have the interconnect fabric route certain data to certain slaves based on address map. If that happens, then the "sniffer" will never get any data to monitor. In that case I will need to make manual connections to the mm slave input across the the "sniffer" and somwhow push that back to the simulation environment.
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Yes, you definitely need the nios->slave connection to happen "across the sniffer". i.e. nios->sniffer->(all your slaves).
My systems normally look like nios->clock_crossing_bridge->(all my slaves) so inserting/removing my own "sniffer" is just two connections between the NIOS and the regular bridge.
If you don't do this, then you are correct that your component will not see any traffic.
i.e. it is not simply a bus that you are tacking wires onto like you might have hoped when you first started.
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