Forum Discussion
Altera_Forum
Honored Contributor
11 years agoOk , using Daves sample master -> slave + test bench and Ted's advice somehow I have the "sniffer" with a mm_master_bfm and a mm_slave_bfm. I believe this was a necessary step prior to running simulation with my hardware environment.
I modified my "sniffer" to match the address and data widths and believe the simulation model is only generated if there are zero errors and zero warnings at the Qsys generate step. I may have been thinking warnings were Ok when they are not. *** Thank you Dave and Ted, for the expert advice. *** I will work with what I have and need to get the "sniffer" slave be able to monitor all traffic from a given master. The address is really a don't care since I am only intereated in write data and completion data at the "sniff" but I need to get Qsys to honor the BridgesToMaster = 1 attribute ... I really need that to happen and not have the interconnect fabric route certain data to certain slaves based on address map. If that happens, then the "sniffer" will never get any data to monitor. In that case I will need to make manual connections to the mm slave input across the the "sniffer" and somwhow push that back to the simulation environment.