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Altera_Forum
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11 years ago

Avalon MM "sniffer" connections in QSYS

I seem to be stuck in connecting a new QSYS component into my system that I have generated. The new component, lets call it bus_tracker, monitors the data output of an Avalon MM master for ...
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
11 years ago

Here is the latest error and ther are no pointers on where to go to resolbe the error.

Error: monitor_1_0: monitor_1 does not support generation for Verilog Simulation. Generation is available for: Quartus Synthesis.

Error: Generation stopped, 9 or more modules remaining

Error: ip-generate failed with exit code 1: 2 Errors, 5 Warnings

Error: There were errors creating the testbench system.