Honored Contributor
Honored ContributorOk replicated into Verilog ... but the I thought the "bridgesToMaster" set to "1" attribute would mean everything was forwarded on ... that appeared on the bridge slave port to the bridge master port. I need this inorder to monitor the all the master output ... but QSYS is trying to make the bridge I have not intersect addresses with the slave ports of intererst.
Do I need to do something else or is the QSYS allocating address map to the bridge ? When I have looked at the AVALON interconnect fabric , the fabric generates a chip select based on the addresws map of the slave ... so ... is this address allocation just a placeholder ? I guess running simulation will say if the address and data makes it to the bridge ? It was ted who was mentioning bridgesToMaster back on page 1. That property seemed to get auto generated when the hw.tcl file was generated. # # connection point mms1 # add_interface mms1 avalon end set_interface_property mms1 addressUnits WORDS set_interface_property mms1 associatedClock clock set_interface_property mms1 associatedReset reset set_interface_property mms1 bitsPerSymbol 8 set_interface_property mms1 bridgesToMaster 1 set_interface_property mms1 burstOnBurstBoundariesOnly false set_interface_property mms1 burstcountUnits WORDS set_interface_property mms1 explicitAddressSpan 0 set_interface_property mms1 holdTime 0 set_interface_property mms1 linewrapBursts false set_interface_property mms1 maximumPendingReadTransactions 0 set_interface_property mms1 readLatency 0 set_interface_property mms1 readWaitTime 1 set_interface_property mms1 setupTime 0 set_interface_property mms1 timingUnits Cycles set_interface_property mms1 writeWaitTime 0 set_interface_property mms1 ENABLED true set_interface_property mms1 EXPORT_OF "" set_interface_property mms1 PORT_NAME_MAP "" set_interface_property mms1 CMSIS_SVD_VARIABLES "" set_interface_property mms1 SVD_ADDRESS_GROUP ""
