Forum Discussion
Altera_Forum
Honored Contributor
11 years agoDave,
Thanks, I have started to work through your qsys_vip example ... I believe you are suggesting to use that environment to test the new "bridge component" that I am to incorporate my Avalon bus sniffer into ? 1. Avalon-MM slave that you connect to the master you are sniffing 2. Avalon-MM master, the pass through connection from the master 3. Avalon-MM slave for performance monitoring registers access I have to get a better understanding of the bridge-> master component ... are we saying that as a bridge, I can connect the bridge slave to the Avalon master port to be monitored and Qsys will just repeat all master traffic to the bridge and the pass through part just propogates say write data, datawrite and be's to my bus tracking logic. The regular Avalon slave interface will access the internal registers that the bus tracking logic drives. I will try tr research the bridge class of components . to see what I can come up with .. what is not obvious is how the read path would be handled for a bridge unless Qsys expects the local slaves or the slaves behind the bridge will respond to reads but not both ... that would be handled by address mapping usually, and I don't have a read path back from my bus sniffer so no read requests would be decoded.