Forum Discussion
Altera_Forum
Honored Contributor
11 years agoSounds like Josy's solution wins.
I had hoped to just specify my sniffer component with a "partial" set of Avalon MM inputs on the sniffer port ie data, data_write and be, but had no success on trying that . I will need to research the "bridge + control port " component. Two additional questions. 1) The local Altera support suggested going into the top.vhdl in Quartus and making the connections I need directly, however , this is awkward since the Quartus rtl is then out of synch with the Qsys. I really want to get Qsys generate to generate the synthesizable code, testbench etc. Would it be correct to say that modifying the Quartus code would break simulation or is there a method for getting the modified rtl design back into the simulation environment ? 2) Even if I don't connect the "sniffer" ports of my new component, in Qsys, when I try to run generate with the testbench and simulation sections selected as well as synthesized code, I get an error mentioning that no BFM or similar exists for the new component ... not sure what this error means .. see below ... any ideas ? Thanks, Bob. Error: get_instance_interface_property top_inst_bus_tracker_0_conduit_flag_bfm CLASS_NAME: No interface named top_inst_bus_tracker_0_conduit_flag_bfm.. Error: can't read "matching_intf()": no such element in array Error: get_instance_interface_property top_inst_bus_tracker_0_conduit_flag_bfm CLASS_NAME: No interface named top_inst_bus_tracker_0_conduit_flag_bfm.. can't read "matching_intf()": no such element in array Error: There were errors creating the testbench system.