Occasional Contributor
Super ContributorThe testbench example is just a guidance and you may need to modify it accordingly to your need. If you want to use any Avalon-MM transactions, i.e., writesingle, read-single, write-burst, and read-burst, please take note that the Avalon-MM read/write single/burst transactions have all been configured for minimum transaction time, i.e., no initial latency, and no idle time between transactions. This setting may not reflect the real Avalon-MM master you use in your particular hardware design, so you may want to adjust these transactions according to your needs. If however your Avalon-MM slaves have been verified with complete code coverage, then these minimum transactions should be acceptable.
And I think it should be possible to write a testbench to specific address as shown in the example provided previously.
Typedef should be supported in System Verilog. You might have do dive deep into what's goes wrong. Check the Questa SIM User Manual.
Occasional ContributorYeah I will look in to that. I just wanted your opinion on the error using array of structures in system verilog.
Moreover, this test bench file must be used as part of test_program.sv file? There was a tb file that was provided with it and only needed to replace that with?
