To do what you are asking, roughly, you add an Avalon-MM Master interface to your custom VHDL component. Connect it to the onchip-memory the same as you have connected the NIOS, and then tell your custom component the base address of the RAM it should write to.
Because you're using Avalon-MM Master, this solution is quite flexible.
But, if you aren't interested in flexibility and are more interested in less labor, it is probably simpler to do something like embed a second dual-port ring buffer RAM inside your custom VHDL component and access it via your IOWR/IORD through your VHDL component.