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gomezramones
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3 years ago

Avalon I2C (Master) Intel FPGA IP

Hi, I am trying to use Avalon I2C (Master) Intel FPGA IP in Qsys but I am not sure how to use the register in this module since there are Control Register to configure the speed or enable the core. ISER to enable ACK and others.

Just to make sure, signals scl_in and sda_in is when the I2C module is reading and scl_oe and sda_oe when is writing, right? In other words, it is the same if I would declare sda :inout and scl : inout?

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