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Hi,
I tried the above method but when master sends the address as BASE + 00 it corresponds to address "0" of the control register..
and when the master sends the address as BASE + 04 instead of corresponding to the address "1" I'm getting "4". What could be the reason for this.
From what I understand the addresses sent by master are not under my control. It is supposed to understand the address alignment and send the address, but it is not happening. Help needed.
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Here are some of the things that I learnt recently...If you are using a tristate bridge then the slave has dynamic addressing...If not then you will have to check the component (edit component and check the deprecated settings) to figure out which alignment the component/slave has. Once you have determined that take a look at the attached document here. It explains how address[0] on FPGA should be connected to slave (page 97)
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