Automatically setting output delays in Stratix 3

Hi,

Still trying to fully understand TimeQuest for proper IO constraining...

I'm using a source-synchronous output scheme, where the output clock is generated from a DDR FF. Using fast output register to force FF in IOE. With the required set_output_delay -min & -max, the fitter can't meet the timings for some pins. But if I manually set some delays (output delays D5 & D6 in Stratix 3 IOE) on the clock output and on other outputs, then my constraints are met.

Interface is running at 200MHz so I would like to minimize the skew between outputs (currently I get near 900ps - too much for my taste).

Any way to let the fitter automatically choose the proper output delay to meet the constraints?

Thanks!

François Choquette

(way more TimeQuest questions to come)