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Our designs are very application specific, so pin names are often not equal between different projects. But if I create a bdf template with the most used pins, I can copy/paste them in the actual design.
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How about making a VHDL top-level that contains *only* a BDF file. That way you could connect your application-specific BDF to a top-level that always has the same pin names.
Alternatively, if the pin names are only one of several names, you could write a "smarter" pin assignments script. I recall writing a test where after design elaboration you can read the top-level pins in a design. You could then compare the list of actual pins, to your pin names list (with multiple names per pin) and then select the appropriate one from the list.
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By the way, do you know the function of tcl command "add_new_io" or "make_input_port". Where do they add the pins? to a netlist?
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I've never used them. If I had this same question, I would simply create a new design and try using the Tcl commands.
Cheers,
Dave
Honored Contributor
