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Altera_Forum's avatar
Altera_Forum
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12 years ago

Automatic IO pin creation

Hello, to explain my question a short word to my design flow. My designs are written in VHDL except the top level. For better readability toplevel is a schematic .bdf file. In some design ...
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
12 years ago

Hi Volker,

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In my opinion your TCL code do the pin assignment of existing pins. e.g IO pin "sc_dq[2] is assigned to FPGA pin D1. What I am looking for is a way to generate IO pins for .bdf toplevel files automatically, so that I can be much faster to do the .bdf

--- Quote End ---

If I understand correctly, you are asking how to automatically add the pin numbers to the BDF.

I do not use BDF, but the following should work; draw your top-level BDF and use pin names that match your Tcl pin assignments script, then run the script and synthesize the design. The Pin Planner view should show that all the pin assignments match your Tcl script. Re-open the BDF file, and Quartus might also re-annotate the BDF to show the pin numbers. If it does not, its not really a problem, since the Pin Planner shows they are correct.

Cheers,

Dave