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Altera_Forum's avatar
Altera_Forum
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12 years ago

Automatic IO pin creation

Hello, to explain my question a short word to my design flow. My designs are written in VHDL except the top level. For better readability toplevel is a schematic .bdf file. In some design ...
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
12 years ago

Thank you Dave,

I use the bdf design flow because our SW- and HW guys are more familar with this "schematic look". If I do toplevel design for simulation purpose I also use all VHDL style.

In my opinion your TCL code do the pin assignment of existing pins. e.g IO pin "sc_dq[2] is assigned to FPGA pin D1. What I am looking for is a way to generate IO pins for .bdf toplevel files automatically, so that I can be much faster to do the .bdf

Regards

Volker