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In some design I have a lot of I/O pins on toplevel. Actually I create the pins by "clicking" in editor.
Is there a possibility to do this work automatically by reading an input file or via TCL script?
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Yes, you can create a Tcl script. Here's the easiest method you can use to get started.
1. Synthesize an existing design that contains pin assignments.
2. Open the Quartus pin planner and confirm that all pins are assigned (no white cells)
3. From the Quartus GUI select "Project->Generate Tcl File for Project"
Now look at the generated Tcl file. That file will contain lines like
set_location_assignment PIN_D1 -to sc_dq
set_location_assignment PIN_T7 -to sram_dq
set_location_assignment PIN_R1 -to sram_addr
set_location_assignment PIN_R14 -to sw
set_location_assignment PIN_D6 -to usb_d
set_location_assignment PIN_E5 -to sc_resetN
set_location_assignment PIN_A7 -to usb_d
set_location_assignment PIN_L16 -to pci_ad
Copy those lines to a file called pinout.tcl, and you can use that from that point on to assign pins for that FPGA.
My personal preference for designs is to have all code in VHDL, and to use a top-level VHDL file that always has all top-level ports, whether the design uses them or not. This allows the pinout file to include all pins, and avoids Quartus warnings about ignored assignments. In your BDF design flow, if your top-level design does not include a pin that your pin assignment script assigns, then Quartus will issue warnings about ignored constraints. You can either live with that, or get a little fancier by running a Tcl script during P&R that first finds all the pins in the current design, and then creates the pin assignments for just those pins. You can use pre-flow/post-flow scripts for this type of fine control.
http://www.altera.com/support/examples/tcl/auto_processing.html Have a play with these ideas, and if you get stuck, come back to the forum and ask for help.
Cheers,
Dave
Honored Contributor
