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Altera_Forum
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17 years ago

automatic firmware revision for VHDL

Dear Experts, i'd like to introduce to my design one register containing a firmware revision. Very probably the firmware revision would be a data when the VHDL code was checked out from the CV...
Altera_Forum's avatar
Altera_Forum
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17 years ago

For subversion I did it with a pre flow tcl script. This scrit is run automatically before compilatio starts. You have to set a variable in the qsf file like this : 

set_global_assignment -name PRE_FLOW_SCRIPT_FILE "quartus_sh:./VersionInfoGenerator/svn.tcl"

In the script I generate a design file (verilog in my case) that contains some registers with the version number. I suspect that for cvs the same must be possible.

See also : http://www.altera.com/support/examples/tcl/tcl-svn-revision.html (http://www.altera.com/support/examples/tcl/tcl-svn-revision.html)

Stefaan