Automated Verilog Module Instantiation

Hello,

Although I do not have knowledge about Python, it is very good that you put your good efforts and got success in that. I really appreciate work you have done to make Verilog Programmers' life easier.

I request you to have a look at http://www.veripool.org/wiki/verilog-mode.

By using /*AUTOINST*/ keyword in Verilog-mode, you can do same thing which you have done. ( Help on this is available at : http://www.veripool.org/projects/verilog-mode/wiki/verilog-mode-help )

Have a Great Day!

Cheers,

Bhaumik