auto gated clock conversion help

Hi,

I am trying to understand how does the automatic clock gating conversion option affect the synthesized design. As an example, I tried the clock gating conversion with the following example code : -

module clock_gating_conversion_project(
input CLOCK_50,
output reg  counter_1,
output reg  counter_2
);
always@(posedge CLOCK_50) begin
	counter_1 <= counter_1 + 1; 
end
wire gated_clock;
clock_gate clock_gate_1(
        .clkout (gated_clock),
        .clk (CLOCK_50),
        .en (counter_1),
        .ti (2'b0));
always@(posedge gated_clock) counter_2 <= counter_2 + 1;
endmodule

The "clock_gate" module is a simple AND gate.

I turned the "Auto Gated Clock Conversion" option "On" in the "Advanced Settings (Synthesis)" tab.

However, I tried the synthesis without defining the clock "CLOCK_50" in the .sdc file using the create_clock statement. In spite of this, Quartus identified that CLOCK_50 was a clock signal getting gated and performed clock gating conversion (I concluded this by seeing that the clocks going to all registers in the post-fitting schematic were free running, and enable signals were used for each flop).

To see what would happen if I define the CLOCK_50 signal as a clock in the .sdc file, I added the following statement to the .sdc file : -

create_clock -period 20.000 -name CLOCK_50 

I re-ran the compilation process with the the Auto Gaed Clock Conversion option turned On, and saw that Quartus had performed the clock gating conversion in this case as well, as expected. However, i saw that the (post-fitting) schematics were different, meaning that the compilation process was not exactly the same.

I think I should consider the compilation with the explicit create_clock constraint as the correct one, but am wondering :-

1) Is the compilation done by Quartus without the explicit create_clock constraint correct as well? It seems to have done some clock gating conversion as the clocks going to all registers are free running with enable signals being used, and

2) Why did Quartus perform the clock gating conversion in the above case, in the absence of the clock definition in the .sdc file, even though the create_clock constraint is supposed to be necessary to perform the conversion?

Any advice would be helpful to make me understand this. Thanks a lot!

Regards,

Akshay