auto gated clock conversion help

The problem that I was having was directly related to using the PLL inside the high-speed transceivers. Apparently there was a bug in Quartus where derive_pll_clocks didn't work correctly in synthesis. The solution for me was to run all the way through fitter. Then write out an SDC file in TimeQuest to get the full name of the PLL clock output. Put the clock information back in my input SDC file using the create_clock command (replacing the derive_pll_clocks). At this point the clocks were all created correctly and I was able to synthesize again with the Auto Gated Clock conversion turned on.