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Altera_Forum
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16 years ago

auto gated clock conversion help

I am trying to implement some ASIC code in an FPGA, and unfortunately the code has gated clocks. Because of the huge clock skew problems this causes I was hoping to use the Auto Gated Clock Conversio...
Altera_Forum's avatar
Altera_Forum
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15 years ago

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Hello Pletz,

We are switching off the clocks to save power. This is an ASIC design which we are trying to run on FPGA.

I've taken your example from another post 

http://www.alteraforum.com/forum/showpost.php?p=15216&postcount=4

Even here the clock gating is not converted into register enable nor anything goes into the report.

Thanks,

Gopal

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Hi,

is the clock gating still necessary on the FPGA ?

I have a small project attached. The clock conversion takes place only:

1. You have switch on the clock conversion under

"Assignments" -> "Settings"-> "Analysis & Synthesis Settings" -> "more Settings"

Auto Gated Clock Conversion ON

2. You have to use TimeQuest as Timing Analyzer

3. You have to define your clocks in TimeQuest

Kind regards

GPK