--- Quote Start ---
Hi,
the Quartus "gate clock conversion" will only work if there are only,
and, or, xor gates in the control of the clock gating. Maybe your Latch is the problem. Try to describe your gating only with gates. What kind of clock gating are you doing? Are the clocks only switched off in order to save power or do you clock dividing ?
Has every clock gating cell different control signals or are there groups which uses the
same signals ? If yes, you can at least reduce the number of gating cells.
Kind regards
GPK
--- Quote End ---
Hello Pletz,
We are switching off the clocks to save power. This is an ASIC design which we are trying to run on FPGA.
I've taken your example from another post
http://www.alteraforum.com/forum/showpost.php?p=15216&postcount=4
Even here the clock gating is not converted into register enable nor anything goes into the report.
Thanks,
Gopal
Honored Contributor
