auto gated clock conversion help

The example code is just the clock gating module (which is instantiated hundreds of times in the ASIC code). The actual en signal input has various logic on it depending on the instance, so it's unfortunately not simply turning the clock on and off each clock cycle.

I would simply instantiate the altclkctrl block, but as I mentioned this module is in the code hundreds of times. Not only would it be quite painful to replace each instance, I don't think there will be enough clocking resources in the FPGA. Can I create several hundred altclkctrl blocks? I guess if that's possible it's at least an option.

What I really wanted to do was switch all the gated clocks to clock enables. That's why I'm asking about the auto gated clock conversion. The problem is that when I turn it on nothing seems to happen. I'm not sure if there is some conflict with another constraint I've set or what.