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Honored Contributor
Honored Contributorauto gated clock conversion help
I am trying to implement some ASIC code in an FPGA, and unfortunately the code has gated clocks. Because of the huge clock skew problems this causes I was hoping to use the Auto Gated Clock Conversio...
Altera_ForumHonored Contributor
Honored ContributorWhy have the gated clock at all? It looks like it's just turning it on and off every other clock cycle. If that's the case, just have the PLL create a clock that's half that rate.
A secondary thing that's pretty straightforward is to instantate the altclkctrl block, which is basically the global driver used between the PLL and global clock tree(this block is always in the design, just inferred if you don't manually enter it). It has an enable signal, which you could drive en_q into(as an enable is basically the same thing as an AND gate). Don't know why the auto gated clock conversion isn't working, but I think either of those should work.
