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Altera_Forum
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10 years ago

Audio Processor Using FPGA SPARTAN 6

I am building an audio processor with effects in my final year project using Spartan 6 and there is a problem i am facing. Since my project guide has left my institute , I am facing a few difficultie...
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
10 years ago

It looks like your problem is the Clock used to generate the ADC signals.

In your example the ADC is clocked with a 44.1 KHz clock whereas the control and data signals are still generated with the 4 MHz clock.

If you change

CLK <= F_CLK_4MHz;

Clk_in <= CLK;

to

CLK <= Clk_mod;

Clk_in <= F_CLK_4MHz;

it should work.