atlmem ddr2 complilation error for stratix III device on quartus 8.0

I am trying to build a nios based system which uses tse mac and ddr2 high performance controller. I generated the system using Quartus 9.1 and successfully generated the sof file. But since C2H is not supported in 9.1 i was forced to the my system back to Quartus 8.0 (since i dont have 9.0 with me). My target FPGA is Startix III device.

I am getting the following error in Analysis & Synthesis stage.

error: input port i of i/o input buffer "nios_tse_net:nios_tse_net_inst|altmemddr:the_altm emddr|altmemddr_controller_phy:altmemddr_controlle r_phy_inst|altmemddr_phy:alt_mem_phy_inst|altmemdd r_phy_alt_mem_phy_siii:altmemddr_phy_alt_mem_phy_s iii_inst|altmemddr_phy_alt_mem_phy_clk_reset_siii: clk|gen_mimic_diff_ibuf.fb_clk_ibuf" must be driven by a top-level pin

error: input port ibar of i/o input buffer "nios_tse_net:nios_tse_net_inst|altmemddr:the_altm emddr|altmemddr_controller_phy:altmemddr_controlle r_phy_inst|altmemddr_phy:alt_mem_phy_inst|altmemdd r_phy_alt_mem_phy_siii:altmemddr_phy_alt_mem_phy_s iii_inst|altmemddr_phy_alt_mem_phy_clk_reset_siii: clk|gen_mimic_diff_ibuf.fb_clk_ibuf" must be driven by a top-level pin

please help me how to solve this.

Thanks in advance

with regards

Prathuesh Prem