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Newbie here.
I need to generate pulses at rising/falling edges of an input signal. I would like to avoid using an internal clock for this application because parts of my system is inherently asynchronous (for one thing, the clock used to count and do other things changes frequency in time). The width of the pulses is not important, I will not be sampling at more than 1Mhz.
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These are some strange design choices, and as a beginner, I would steer clear. Unless you know what you're doing, asynchronous systems are going to be a headache. WHy is the design asynchronous? why does the clock change frequency?
You would have a much easier life if you synchronised the design to a single, stable clock. Apart from the fact this is how FPGAs are designed to work, you will have more tools and help at your disposal.
Honored Contributor
