Forum Discussion
Altera_Forum
Honored Contributor
8 years agoSynthesis is the act of turning a design into something that can run in hardware. Simulation is simulating the function of a design in a simulation tool. You can do a lot of things in a design for simulation that you can't do in a synthesizable design like define time delays, since time delays in hardware are determined by the hardware itself, not how you code it.
For synthesis, you could just write: if (rising_edge(dclk)) then gclk <= NOT gclk; end if;