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Altera_Forum's avatar
Altera_Forum
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16 years ago

Asynchronous clocks in Quartus

Im trying to model ATA device interface unsing DE1 with Cyclone II on board.PIO modes seams to be book example of asynchronous memory read write - there is asynchronous signal which enables data.

My first idea was to sample all inputs in respect to PLL clock (100Mhz) and keep all design fully synchronous, that works fine with slow transfer modes. But for faster transfer modes 100Mhz resolution is not enough, increasing PLL multiplayers beyond 100Mhz causes problems.

Summarising question is: Is it possible to:

Define asynchronus write/read enable signal as individual clock with fmax equivalent to shortest stable state of signal in Classic Time Analyser even if that signal isnt assigned to Dedicated Clock I/O and expect such clock to work just fine - be used in VHDL event statments.

Thanks in advance for response.

1 Reply

  • Altera_Forum's avatar
    Altera_Forum
    Icon for Honored Contributor rankHonored Contributor
    16 years ago

    It's often necessary to use additional external clocks in designs, and it's not always possible to assign dedicated clock inputs for these signals. Serial or parallel slave interfaces are a typical example.

    You can expect reliable operation of these design parts, but making the data cross the clock domains consistently requires some effort.