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Altera_Forum's avatar
Altera_Forum
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15 years ago

asynchronous bus implementation.

i am tring to implement an external bus interface which is connected to ARM chip.

oe, we, ce, addr, data signals were provided by MCU.

i have to drive my registers with 25Mhz internal clock.

so, there are two clock domains. metastable problems must be solved.

but i want to speed up the interface's r/w speed, which makes the external bus work about 50ns.

ce is active about 50ns.

we/oe remains 30ns active.

ce comes 20ns ahead of we/oe.

we/oe was selected as clock.

this design would need a two clock synchrounous mechenism for those signals.

it would be a long time for me, because some register have to be read immediately after write.

is there any one-clock synchronizer exist?

3 Replies

  • Altera_Forum's avatar
    Altera_Forum
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    15 years ago

    What's a "one-clock synchronizer"?

    CE length of only 50 ns either requires oversampling the bus at a high rate, I guess at least 100 MHz, or operating the interface synchronous to the ARM clock. Some ARM variants are exposing a synchronous interface with a clock, otherwise the clock would need to be synthesized from the ARM input clock, and most likely phase synchronized to the bus signals.

    Using OE and WE as clocks doesn't seem a straightforward solution to handle the bus.

    We usually try to live with a slower bus, inserting some wait states.
  • Altera_Forum's avatar
    Altera_Forum
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    15 years ago

    one-clock synchronizer is a synchronizer need only one clock to synchronize clock domain.

    it is compared to two filp flop synchronizer, which need two clock to synchronize.
  • Altera_Forum's avatar
    Altera_Forum
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    15 years ago

    If the clock is slow enough, you can utilize both edges for the synchronizer, instead of introducing a faster oversampling clock. It's against a clear, straightforward design, but may be useful anyway.