asynchronous bus implementation.

What's a "one-clock synchronizer"?

CE length of only 50 ns either requires oversampling the bus at a high rate, I guess at least 100 MHz, or operating the interface synchronous to the ARM clock. Some ARM variants are exposing a synchronous interface with a clock, otherwise the clock would need to be synthesized from the ARM input clock, and most likely phase synchronized to the bus signals.

Using OE and WE as clocks doesn't seem a straightforward solution to handle the bus.

We usually try to live with a slower bus, inserting some wait states.