Honored ContributorHello everybody,
I'm doing a FLL design in VHDL. It works on Xilinx ISE by using the ASYNC_REG attribute on the proper signals. Thus, I would like to know if something equivalent exists for Altera FPGAs (I am using Libero). Otherwise, does anyone know how I can fix this kind of problem ? Thanks, M. Bund
Honored ContributorWhat is an ASYNC_REG when it's at home?
What exactly are you planning on doing with a Libero? Is this the Libero SoC from Microsemi? you realise this isnt Altera?Honored ContributorWell, sorry I meant Quartus.
From the Xilinx Constraints guide : "The ASYNC_REG timing constraint improves the behavior of asynchronously clocked data for simulation. Specifically, it disables 'X' propagation during timing simulation. In the event of a timing violation, the previous value is retained on the output instead of going unknown." I am looking for the same thing.Honored ContributorOk. I see what you mean
The equivolent would be set_false_path <regA> <regB>, but you'll need to read up on SDC format on how to search for the registers.
