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Altera_Forum
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11 years ago

ASYNC_REG attribute for Altera FPGA

Hello everybody, I'm doing a FLL design in VHDL. It works on Xilinx ISE by using the ASYNC_REG attribute on the proper signals. Thus, I would like to know if something equivalent exists fo...
Altera_Forum's avatar
Altera_Forum
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11 years ago

Well, sorry I meant Quartus.

From the Xilinx Constraints guide : "The ASYNC_REG timing constraint improves the behavior of asynchronously clocked data for simulation. Specifically, it disables 'X' propagation during timing simulation. In the event of a timing violation, the previous value is retained on the output instead of going unknown."

I am looking for the same thing.