Assign SDC files on each VHDL component project

Thank you everyone,

Daixiwen, nplttr, in my FPGA design data from main input is processed in one component, the result of processed data is passed again into next component using source synchronous data transfer, and it repeated again until four step before it passed to final output. Are you sure we only need to constraint only in top level entity?

Constraining false path and multicyles will be difficult(I think) especially in a design which each component operation depend on output of others components or main input. Internal component design operation is not based on the time, but input (in this case, I connect it to a controller which will send instruction to my design, and It will send instruction as It pleased).

Jobsyb,

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I think what rochmadp is asking is: is there a way to automatically incorporate .sdc files from a lower level in the top level?

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yes, that is what I mean, so basically we can't incorporate original lower level sdc files? We need to recreate it based on original sdc files for top level entity? Is there any automatically way to do it? or it already included in altera software or timequest sofware?

Thank you, and sorry for many question :), I'm still learning on this things,...