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Altera_Forum's avatar
Altera_Forum
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14 years ago

Assign SDC files on each VHDL component project

Hi everyone, I need help here. I have a FPGA VHDL project, the project consist of several independent component (also made in VHDL) which are arranged into a single large project (top leve...
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
14 years ago

I think it is better to constrain only the top level entity.

This allows Timequest to automatically optimize the internal components.