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Altera_Forum
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14 years ago

Assign SDC files on each VHDL component project

Hi everyone, I need help here. I have a FPGA VHDL project, the project consist of several independent component (also made in VHDL) which are arranged into a single large project (top leve...
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
14 years ago

You should only constrain the FPGA's pins in the SDC file, all the internal signals timings between two VHDL components are automatically handled by Timequest.

The only component specific timing constrains you way need to add at a component level are multicycles and false paths.