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Altera_Forum's avatar
Altera_Forum
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16 years ago

Assertion error while synthesizing in Quartus2 9.0

Hello,

I'm new to Altera devices and Quartus.

I'm retargetting a big hierarchical design with Memory Wrappers containing behavioral code for FPGA flow.

While synthesizing, the tools infers the memory but stops with following error message:

"Assertion error: The current megafunction is configured for use with the clear box feature and cannot be used when the clear box feature is disabled"

All the documentation, forum search results, knowledge-base refer to single note:

http://www.altera.com/support/kdb/solutions/rd09082006_596.html?gsa_pos=1&wt.oss_r=1&wt.oss=clear%20box%20is%20disabled (http://www.altera.com/support/kdb/solutions/rd09082006_596.html?gsa_pos=1&wt.oss_r=1&wt.oss=clear%20box%20is%20disabled)

But, am not sure how to enable/disable "clear box" feature from the Quartus2 GUI wizards.

Please let me know whether am doing it right or some steps are missing which must be followed.

Additionally, all the memory wrappers (VHDL) have "attributes" for Xilinx FPGAs; which are "WARNed out" by quartus, and ignored. I think this may not be causing the problem.

Thanks in advance

-aditya

3 Replies

  • Altera_Forum's avatar
    Altera_Forum
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    Hello,

    Why not try to remove all the .tdf files as explained it the Support? Perhaps it will work.

    Isaac Campos
  • Altera_Forum's avatar
    Altera_Forum
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    --- Quote Start ---

    Hello,

    Why not try to remove all the .tdf files as explained it the Support? Perhaps it will work.

    Isaac Campos

    --- Quote End ---

    Thanks Isaac,

    Do you mean to delete the 'auto' generated *.tdf files from "db/" folder!

    I've done that and rerun the Synthesis flow; but those files got regenerated and same error occured!

    As I have pure HDL code and no other generated IP/Memory from quartus tool. All the RAM is INFERRED from VHDL code.

    Is there anything other can be done which is not like deleting auto-generated files? For example, without modifying the HDL code; any command like switches, etc.

    Thanks again.

    -aditya
  • Altera_Forum's avatar
    Altera_Forum
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    I got a similar error: (.... protects the innocent).

    Error: MGL_INTERNAL_ERROR: Assertion failure inside rtl_body at

    /build/swbuild/SJ/nightly/9.1sp1/304/l32/p4/quartus/.....cpp:1964

    CAUSE : The condition in MGL_ASSERT () failed at...

    Error: Assertion error: The current megafunction is configured for use

    with the clear box feature and cannot be used when the clear box

    feature is disabled File:

    ..../9.1/quartus/libraries/megafunctions/altmult_add.tdf Line: 1540

    Turns out I had generated some IP (in this case the SOPC) using

    Stratix IV, but was targeting the top at a Stratix II. Bogus move for

    sure, but the help message could've been better.

    Getting the families to line up fixed the error.