I managed to bypass the problem so i'm posting it for future seekers:
I changed the ALTERA ASMI core vhd file manually:
-----------------------------------------------------------
old code:
PROCESS (clkin_wire, end_ophdly)
BEGIN
IF (end_ophdly = '1') THEN ncs_reg <= '0';
ELSIF (clkin_wire = '0' AND clkin_wire'event) THEN
IF (wire_ncs_reg_ena = '1') THEN ncs_reg <= '1';
END IF;
END IF;
END PROCESS;
------------------------------------------------------------
new code:
PROCESS (clkin_wire, end_ophdly)
BEGIN
IF (end_ophdly = '1') THEN ncs_reg <= '1';
ELSIF (clkin_wire = '0' AND clkin_wire'event) THEN
IF (wire_ncs_reg_ena = '1') THEN ncs_reg <= '0';
END IF;
END IF;
END PROCESS;
-------------------------------------------------------------
now the design is working ;)