Forum Discussion
Altera_Forum
Honored Contributor
9 years ago --- Quote Start --- I've captured the screenshots of each PHY configuration to see how-to consolidate the 6 Gbps config. I guess I don't understand enough to configure the "custom PHY" to do neither double-rate i.e. "wide FPGA Fabric config" nor 8b/10B encoding enabling. . --- Quote End --- I think I found the reference design you were mentioning. It is definitely not straightforward from TTK 2 Gbps reference design to 6 Gbps and this should be included in TTK links. The Altera wiki doesn't show this link in normal places but searching for Seriallite gave a result. http://www.alterawiki.com/wiki/file:arriaiigx_devkit_seriallite_4_lanes_6250mbps.zip Now the challenge seem to be running the design internally in X95 as a standalone. I don't have external memory in my design. If you have suggestions, comments or anything, please let me know. Thanks, Zeki