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Altera_Forum
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9 years ago

Arria II GX TTK configuration problem running at 6Gbps

Hi all,

I am trying to get the TTK to work @ 6 Gbps with ARria-II GX and having difficulties. I was wondering of anyone has suggestions or a TTK project with 6 Gbps Arria II GX to share.

Altera has an example design for 2 Gbps for Arria II GX and that works.

Modifying to run design at 6 Gbps I assume is with the following steps, and I am unable to successfully complete it.

1. Test existing design as it is @ 2 Gbps. (Quartus 14.1, 15.1, 16.0 all works)

1. Take 2 Gbps design to use 8b/10b encoder (HW module) and test it. (Sometimes work. Synchronization issue. After startup it either works or not... Seemingly random)

2. Change datapath to 16 bit wide and test it. (Doesn't work. Observed problems with custom PHY megacore. Although I configure datapath to 8/16/32 etc. widths, I/Os seem to be still recognized as 8 bits. Quartus recognizes it and inserts its own adapters while compiling.)

3. Change clock rate to 6 Gbps. (Never got there).

Thank You,

Zeki

6 Replies

  • Altera_Forum's avatar
    Altera_Forum
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    9 years ago

    I assume you're using I3 speed grade devices?

    We use Arria II GX I3 devices for SATA 3 (6.0 Gbps) and did some testing with the TTK a few years ago up to 6.375Gbps between our board and an Arria II GX dev kit with no problems. Can't help you beyond confirming that it works. That was probably with Quartus 13.0.
  • Altera_Forum's avatar
    Altera_Forum
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    9 years ago

    Thanks for quick reply. I am using Arria II GX 95 with I3 speed grade.

    I don't understand the requirements for 6 Gbps operation and Transceiver toolkit interaction and specifically the custom_PHY.

    I have a working design running at 6 Gbps (CPRI) already. The problem we are having is errors in the link. Looking at custom PHY and CPRI interface PHY, fields don't match either.

    It feels like Arria-II GX is an orphan in terms of explaining the TTK operations.

    I thought I would do the following changes to get it working with 6 Gbps.

    1. Change FPGA Fabric to Transceiver with to 16 bits.

    2. Enable 8B/10B encoder/decoder

    3. Set word alignment pattern to K28.5(-?)

    4. Set datapath to 16 bits.

    I don't mind using any other PHY to test the performance @ 6 Gbps such as SATA but there is not much to go with Arria II GX. All examples are for 1-2 Gbps.

    How did you configure the transceivers for SATA 3.0 on Arria GX II?
  • Altera_Forum's avatar
    Altera_Forum
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    9 years ago

    We bought a SATA core (Intelliprop) and the transceivers are buried in the core. Sorry, again not much help. I'll take a look at the TTK stuff tomorrow and see if I can remember what we did. I recall it being pretty easy to use once I figured out the interface. Just picked a speed and then had it sweep all parameters.

  • Altera_Forum's avatar
    Altera_Forum
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    9 years ago

    --- Quote Start ---

    We bought a SATA core (Intelliprop) and the transceivers are buried in the core. Sorry, again not much help. I'll take a look at the TTK stuff tomorrow and see if I can remember what we did. I recall it being pretty easy to use once I figured out the interface. Just picked a speed and then had it sweep all parameters.

    --- Quote End ---

    I've captured the screenshots of each PHY configuration to see how-to consolidate the 6 Gbps config.

    I guess I don't understand enough to configure the "custom PHY" to do neither double-rate i.e. "wide FPGA Fabric config" nor 8b/10B encoding enabling.

    Attached...

    The CPRI PHY is inside IP and separate RX & TX configs.

    Thank you for quick reply BTW.
  • Altera_Forum's avatar
    Altera_Forum
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    9 years ago

    --- Quote Start ---

    I've captured the screenshots of each PHY configuration to see how-to consolidate the 6 Gbps config.

    I guess I don't understand enough to configure the "custom PHY" to do neither double-rate i.e. "wide FPGA Fabric config" nor 8b/10B encoding enabling.

    .

    --- Quote End ---

    I think I found the reference design you were mentioning. It is definitely not straightforward from TTK 2 Gbps reference design to 6 Gbps and this should be included in TTK links. The Altera wiki doesn't show this link in normal places but searching for Seriallite gave a result.

    http://www.alterawiki.com/wiki/file:arriaiigx_devkit_seriallite_4_lanes_6250mbps.zip

    Now the challenge seem to be running the design internally in X95 as a standalone. I don't have external memory in my design.

    If you have suggestions, comments or anything, please let me know.

    Thanks,

    Zeki
  • Altera_Forum's avatar
    Altera_Forum
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    9 years ago

    I attached one of the projects we used for 6Gbps testing. This project targeted the Arria II GX 6Gbps dev kit. There was a corresponding project that targeted our custom board. I tried to archive the project using Quartus but for some reason the Quartus archive utility doesn't handle Qsys projects very well (lots of missing files). So instead I used WinRAR to package up the whole project folder. I hope this helps.

    Bob

    Edit: The site would not let me upload a .rar file so I changed the extension to .zip. You may have to change it back to .rar on your end.