New Contributor
Regular ContributorReassigned to EMIF team.
New ContributorThe number of pins of 3GBANK is 47, and the hard memory controller is not displayed in the software, so can 3G be used as the address and command bank? Since I found that the 3G bank of 10ax115rf40 has no hard memory controller, I would like to ask, so yesterday I used 3H bank as the address and command bank, 3G bank as the data bank, and then similar questions are as follows:
Error (14566): The Fitter cannot place 1 periphery component(s) due to conflicts with existing constraints (1 EMIF_GROUP(s)). Fix the errors described in the submessages, and then rerun the Fitter. The Intel FPGA Knowledge Database may also contain articles with information on how to resolve this periphery placement failure. Review the errors and then visit the Knowledge Database at https://www.altera.com/support/support-resources/knowledge-base/search.html and search for this specific error message number.
Error (175020): The Fitter cannot place logic EMIF_GROUP that is part of Arria 10 External Memory Interfaces DDR0_altera_emif_180_d2i6ggq in region (142, 169) to (142, 207), to which it is constrained, because there are no valid locations in the region for logic of this type.
Info (14596): Information about the failing component(s):
Info (175028): The EMIF_GROUP name(s): EMIF_1_DDR0_altera_emif_180_d2i6ggq
Info (175015): The I/O pad a_emif_0_mem_mem_cs_n[0] is constrained to the location PIN_K20 due to: User Location Constraints (PIN_K20)
Info (14709): The constrained I/O pad is contained within a pin, which is contained within a ADDR_CMD_GRP, which is contained within this EMIF_GROUP
New Contributor
@niceflower wrote:The number of pins of 3GBANK is 47, and the hard memory controller is not displayed in the software, so can 3G be used as the address and command bank? Since I found that the 3G bank of 10ax115rf40 has no hard memory controller, I would like to ask, so yesterday I used 3H bank as the address and command bank, 3G bank as the data bank, and then similar questions are as follows:
Error (14566): The Fitter cannot place 1 periphery component(s) due to conflicts with existing constraints (1 EMIF_GROUP(s)). Fix the errors described in the submessages, and then rerun the Fitter. The Intel FPGA Knowledge Database may also contain articles with information on how to resolve this periphery placement failure. Review the errors and then visit the Knowledge Database at https://www.altera.com/support/support-resources/knowledge-base/search.html and search for this specific error message number.
Error (175020): The Fitter cannot place logic EMIF_GROUP that is part of Arria 10 External Memory Interfaces DDR0_altera_emif_180_d2i6ggq in region (142, 169) to (142, 207), to which it is constrained, because there are no valid locations in the region for logic of this type.
Info (14596): Information about the failing component(s):
Info (175028): The EMIF_GROUP name(s): EMIF_1_DDR0_altera_emif_180_d2i6ggq
Info (175015): The I/O pad a_emif_0_mem_mem_cs_n[0] is constrained to the location PIN_K20 due to: User Location Constraints (PIN_K20)
Info (14709): The constrained I/O pad is contained within a pin, which is contained within a ADDR_CMD_GRP, which is contained within this EMIF_GROUP
How to realign EMIF GROUP? Is there a tutorial on the official website? Some of the problems I have found are that 10ax115RF40 has a problem with the amount of DDR4 using 40bit data bits, which is 1 on page 200 of a10handbook, but 2 calculated on the emif-device-selector table.
